1. Field of the Invention
The present invention relates to a flash EEPROM and particularly to a nonvolatile semiconductor memory device, which is capable of saving its overwrite state.
2. Description of the Related Art
FIG. 20 is a circuit diagram showing a cell structure of a NAND-structured flash memory. In the NAND-structured flash memory, memory cells M1 to M16, each comprising a MOS transistor having a floating gate and a control gate, are connected in series. One end of a group of memory cells are connected to a bit line BL through a select transistor Q11, and the other end is connected to a common source line S through a select transistor Q12. Each transistor is formed on the same well W. The control gate of each of memory cells M1 to M16 is connected to each of word lines WL1 to WL16. The gate of the select transistor Q11 is connected to a select line SL1. The control gate of the select transistor Q12 is connected to a select line SL2.
In the NAND-structured flash memory, a state in which data "1" is normally stored is called "erase state", and a state in which data "0" is stored is called "write state." The memory cell storing data "0" has a threshold voltage of 0 V or more to 5 V or less, and the memory cell storing data "1" has a threshold voltage of 0 V or less. As shown in FIG. 21A, a state in which the threshold voltage of the memory cell storing data "1" is shifted in a positive direction to store data "0" is called "writing operation." As shown in FIG. 21B, a state in which the threshold voltage of the memory cell storing data "0" is shifted in a negative direction to store data "1" is called "erasing operation."
FIG. 22 shows a voltage to be applied to the memory cell at the time of each of the reading operation, the erasing operation, and the writing operation.
For example, at the time of the reading operation, the bit line BL is precharged to 5 V, and set to be in a floating state. Thereafter, 5 V is applied to the select line SL1, 0 V is applied to the word line WL of the selected memory cell, 5 V is applied to the word line WL of a non-selected memory cell, 5 V is applied to the select line SL2, 0 V is applied to the well W, and 0 V is applied to a common source line S. As a result, all transistors except the selected memory cell are turned on. In a case where data "0" is stored in the selected memory cell, the memory cell becomes non-conductive, and the potential of the bit line BL, which is 5 V, is unchanged. In a case where data "1" is stored in the selected memory cell, the memory cell becomes conductive, and the bit line BL is discharged and the potential is decreased. The potential of the bit line is detected, and thereby data is sensed.
At the time of the erasing operation, the bit line BL is opened, 0 V is applied to the select line SL1, 0 V is applied to the word line WL of the memory cell, 0 V is applied to the select line SL2, 18 V is applied to the well W, and 18 V is applied to the common source line S. As a result, a tunnel current is supplied between the floating gate and the well through a gate insulation film, and the threshold voltage becomes 0 V or less.
At the time of the writing operation, a different voltage is applied depending on writing data. More specifically, in a case where data "0" is written, 0 V is applied to the bit line BL. In a case where data "1" is written, 9 V is applied to the bit line BL. Then, 11 V is applied to the select line SL1, 18 V is applied to the word line WL of the selected memory cell, 9 V is applied to the word line WL of the non-selected memory cell, 0 V is applied to the select line SL2, 0 V is applied to the well W, and 0 V is applied to the common source line S. As a result, all transistors, including the select transistor Q11 to the memory cell M16, become conductive to have the same potential as the bit line.
Therefore, in the memory cell in which 0 V is applied to the bit line BL, the voltage between the channel and the control gate becomes high, e.g., 18 V, and the threshold voltage of the memory cell is shifted in the positive direction by the tunnel current. In the memory cell in which 9 V is applied to the bit line BL, since only 9 V is applied between the channel and the control gate, the shift of the threshold voltage to the positive direction is restrained. Such a voltage of 9 V is called a write prohibition voltage.
In the nonvolatile semiconductor memory device, since data is written by use of the tunnel current, a writing speed is varied, depending on each memory cell. Due to this, even if the writing time is the same in each memory cell, the threshold voltage of a certain memory cell ranges from 0 V to 5 V, and there is a case in which the threshold voltage of the other memory cell exceeds 5 V.
As mentioned above, in the NAND-structured flash memory, 5 V is applied to the word line of the non-selected memory at the time of the reading operation, so that the memory cell is turned on. However, if the threshold voltage of a certain memory cell exceeds 5 V, the memory cell is maintained in an off state. As a result, a current path is interrupted by the certain memory cell, data of all other memory cells, which are connected to the certain memory cell in series, cannot be read.
In order to avoid generating such a problem, there is used a method in which the writing time is divided into a short time period to repeat a cycle of writing.fwdarw.verifying.fwdarw.data setting for rewriting.fwdarw.writing.fwdarw.verifying.fwdarw.data setting for rewriting . . . The memory in the threshold voltage is sufficiently increased by the verifying operation and sets rewriting data not to perform the writing operation in a next cycle.
In other words, in a case where the threshold voltage of the selected memory cell MC to be written is -1 V at the end of the first writing operation as shown in FIG. 23A, the rewriting operation is performed and the threshold voltage ranges from 0 V to 5 V as shown in FIG. 23B. As a result, the writing operation of the cell whose writing speed is high is rapidly ended, and the threshold voltage is not increased thereafter.
However, as shown in FIG. 23C, there is a case in which the threshold voltage of the selected memory cell MC is sharply increased at the time of the first writing operation and exceeds the upper limit of 5 V. In this case, the writing operation is normally ended at the time of the verifying operation. However, data of all other memory cells, which are connected to the memory cell in series, cannot be read as mentioned above. Such a phenomenon occurs in a case where the writing and erasing are repeatedly performed, and it is difficult to screen the memory cell by a test.